View EE87C196MC_6597687.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. april 1994 copyright ? intel corporation, 1995 order number: 270946-005 8xc196mc industrial motor control microcontroller 87c196mc 16 kbytes of on-chip otprom * 87c196mc, rom 16 kbytes of on-chip factory-programmed otprom 80c196mc romless y high-performance chmos 16-bit cpu y 16 kbytes of on-chip otprom/ factory-programmed otprom y 488 bytes of on-chip register ram y register to register architecture y up to 53 i/o lines y peripheral transaction server (pts) with 11 prioritized sources y event processor array (epa) e 4 high speed capture/compare modules e 4 high speed compare modules y extended temperature standard y two 16-bit timers with quadrature decoder input y 3-phase complementary waveform generator y 13 channel 8/10-bit a/d with sample/ hold with zero offset adjustment h/w y 14 prioritized interrupt sources y flexible 8-/16-bit external bus y 1.75 m s 16 x 16 multiply y 3 m s 32/16 divide y idle and power down modes the 8xc196mc is a 16-bit microcontroller designed primarily to control 3 phase ac induction and dc brush- less motors. the 8xc196mc is based on intel's mcs 96 16-bit microcontroller architecture and is manufac- tured with intel's chmos process. the 8xc196mc has a three phase waveform generator specifically designed for use in ``inverter'' motor control applications. this peripheral allows for pulse width modulation, three phase sine wave generation with minimal cpu intervention. it generates 3 complementary non-overlapping pwm pulses with resolutions of 0.125 m s (edge trigger) or 0.250 m s (centered). the 8xc196mc has 16 kbytes on-chip otprom/rom and 488 bytes of on-chip ram. it is available in three packages; plcc (84-l), sdip (64-l) and eiaj/qfp (80-l). note that the 64-l sdip package does not include p1.4, p2.7, p5.1 and the clkout pins. operational characteristics are guaranteed over the temperature range of b 40 cto a 85 c. the 87c196mc contains 16 kbytes on-chip otprom. the 83c196mc contains 16 kbytes on-chip rom. all references to the 80c196mc also refers to the 83c196mc and 87c196mc unless noted. * otprom (one time programmable read only memory) is the same as eprom but it comes in an unwindowed package and cannot be erased. it is user programmable.
8xc196mc 270946 1 note: connections between the standard i/o ports and the bus are not shown. figure 1. 87c196mc block diagram 2
8xc196mc processinformation thisdeviceismanufacturedonpx29.5,achmos iii-eprocess.additionalprocessandreliabilityinfor- mationisavailableinthe intel ? quality system handbook. 270946 16 example: n87c196mc is 84-lead plcc otprom, 16 mhz. for complete package dimensional data, refer to the intel packaging handbook (order number 240800). note: 1. eproms are available as one time programmable (otprom) only. figure 3. the 8xc196mc family nomenclature thermal characteristics package i ja i jc type plcc 35 c/w 13 c/w qfp 56 c/w 12 c/w sdip tbd tbd all thermal impedance data is approximate for static air conditions at 1w of power dissipation. values will change depending on operation conditions and application. see the intel packaging handbook (order number 240800) for a description of intel's thermal impedance test methodology. 8xc196mc memory map description address external memory or i/o 0ffffh 06000h internal rom/eprom or external 5fffh memory (determined by ea ) 2080h reserved. must contain ffh. 207fh (note 5) 205eh pts vectors 205dh 2040h upper interrupt vectors 203fh 2030h rom/eprom security key 202fh 2020h reserved. must contain ffh. 201fh (note 5) 201ch reserved. must contain 20h 201bh (note 5) ccb1 201ah reserved. must contain 20h 2019h (note 5) ccb0 2018h reserved. must contain ffh. 2017h (note 5) 2014h lower interrupt vectors 2013h 2000h sfr's 1fffh 1f00h external memory 1effh 0200h 488 bytes register ram (note 1) 01ffh 0018h cpu sfr's (notes 1, 3) 0017h 0000h notes: 1. code executed in locations 0000h to 03ffh will be forced external. 2. reserved memory locations must contain 0ffh unless noted. 3. reserved sfr bit locations must contain 0. 4. refer to 8xc196kc for sfr descriptions. 5. warning: reserved memory locations must not be written or read. the contents and/or function of these lo- cations may change with future revisions of the device. therefore, a program that relies on one or more of these locations may not function properly. 3
8xc196mc 270946 2 note: * the pin sequence is correct. the 64-lead sdip package does not include the following pins: p1.4/ach12, p2.7/compare3, p5.1/inst, clkout. figure 2. 64-lead shrink dip (sdip) package 4
8xc196mc 270946 3 note: nc means no connect. do not connect these pins. figure 3. 84-lead plcc package 5
8xc196mc 270946 4 note: nc means no connect. do not connect these pins. figure 4. 80-lead shrink eiajqfp (quad flat pack) 6
8xc196mc pin descriptions (alphabetically ordered) symbol function ach0 ach12 analog inputs to the on-chip a/d converter. ach0 7 share the input pins (p0.0 p0.7, p1.0 p1.4) with p0.0 7 and ach8 12 share pins with p1.0 4. if the a/d is not used, the port pins can be used as standard input ports. angnd reference ground for the a/d converter. must be held at nominally the same potential as v ss . ale/adv (p5.0) address latch enable or address valid output, as selected by ccr. both options allow a latch to demultiplex the address/data bus on the signal's falling edge. when the pin is adv , it goes inactive (high) at the end of the bus cycle. ale/adv is active only during external memory accesses. can be used as standard i/o when not used as ale/adv. bhe /wrh (p5.5) byte high enable or write high output, as selected by the ccr. bhe will go low for external writes to the high byte of the data bus. wrh will go low for external writes where an odd byte is being written. bhe /wrh is activated only during external memory writes. buswidth (p5.7) input for bus width selection. if ccr bits 1 and 2 e 1, this pin dynamically controls the bus width of the bus cycle in progress. if buswidth is low, an 8-bit cycle occurs. if it is high, a 16-bit cycle occurs. this pin can be used as standard i/o when not used as buswidth. capcomp0 capcomp3 the epa capture/compare pins. these pins share p2.0 p2.3. if not used (p2.0 p2.3) for the epa, they can be configured as standard i/o pins. clkout output of the internal clock generator. the frequency is (/2 of the oscillator frequency. it has a 50% duty cycle. compare0 compare3 the epa compare pins. these pins share p2.4 p2.7. if not used for the (p2.4 p2.7) epa, they can be configured as standard i/o pins. ea external access enable pin. ea e 0 causes all memory accesses to be external to the chip. ea e 1 causes memory accesses from location 2000h to 5fffh to be from the on-chip otprom/qrom. ea e 12.5v causes execution to begin in the programming mode. ea is latched at reset. extint a programmable input on this pin causes a maskable interrupt vector through memory location 203ch. the input may be selected to be a positive/negative edge or a high/low level using wg e protect (1fceh). inst (p5.1) inst is high during the instruction fetch from the external memory and throughout the bus cycle. it is low otherwise. this pin can be configured as standard i/o if not used as inst. nmi a positive transition on this pin causes a non-maskable interrupt which vectors to memory location 203eh. if not used, it should be tied to v ss . may be used by intel evaluation boards. port0 8-bit high impedance input-only port. also used as a/d converter inputs. port0 pins should not be left floating. these pins also used to select programming modes in the otprom devices. port1 5-bit high impedance input-only port. p1.0 p1.4 are also used as a/d converter inputs. in addition, p1.2 and p1.3 can be used as timer 1 clock input and direction select respectively. port2 8-bit bidirectional i/o port. all of the port2 pins are shared with the epa i/o pins (capcomp0 3 and compare0 3). port3 8-bit bidirectional i/o ports with open drain outputs. these pins are shared port4 with the multiplexed address/data bus which uses strong internal pullups. port5 8-bit bidirectional i/o port. 7 of the pins are shared with bus control signals (ale , inst, wr ,rd , bhe , ready, buswidth). can be used as standard i/o. 7
8xc196mc pin descriptions (alphabetically ordered) (continued) symbol function port6 8-bit output port. p6.6 and p6.7 output pwm, the others are used as the wave form generator outputs. can be used as standard output ports. pwm0, pwm1 programmable duty cycle, programmable frequency pulse width modulator (p6.6, p6.7) pins. the duty cycle has a resolution of 256 steps, and the frequency can vary from 122 hz to 31 khz (16 mhz input clock). pins may be configured as standard output if pwm is not used. rd (p5.3) read signal output to external memory. rd is low only during external memory reads. can be used as standard i/o when not used as rd . ready (p5.6) ready input to lengthen external memory cycles. if ready e 0, the memory controller inserts wait states until the next positive transition of clkout occurs with ready e 1. can be used as standard i/o when not used as ready. reset reset input to and open-drain output from the chip. held low for at least 16 state times to reset the chip. input high for normal operation. reset has an ohmic internal pullup resistor. t1clk timer 0 clock input. this pin has two other alternate functions: ach10 and (p1.2) p1.2. t1dir timer 0 direction input. this pin has two other alternate functions: ach11 and (p1.3) p1.3. v pp the programming voltage is applied to this pin. it is also the timing pin for the return from power down circuit. connect this pin with a 1 m f capacitor to v ss anda1m x resistor to v cc . if the power down feature is not used, connect the pin to v cc . wg1 wg3/wg1 wg3 3 phase output signals and their complements used in motor control (p6.0 p6.5) applications. the pins can also be configured as standard output pins. wr /wrl (p5.2) write and write low output to external memory. wr will go low every external write. wrl will go low only for external writes to an even byte. can be used as standard i/o when not used as wr /wrl . xtal1 input of the oscillator inverter and the internal clock generator. this pin should be used when using an external clock source. xtal2 output of the oscillator inverter. pmode determines the eprom programming mode. (p0.4 7) pact a low signal in auto programming mode indicates that programming is in (p2.5) process. a high signal indicates programming is complete. pale a falling edge in slave programming mode and auto configuration byte (p2.1) programming mode indicates that ports 3 and 4 contain valid programming address/command information (input to slave). prog a falling edge in slave programming mode begins programming. a rising edge (p2.2) ends programming. pver a high signal in slave programming mode and auto configuration byte (p2.0) programming mode indicates the byte programmed correctly. cpver cumulative program verification. pin is high if all locations since entering a (p2.6) programming mode have programmed correctly. ainc auto increment. active low input enables the auto increment mode. auto (p2.4) increment will allow reading or writing of sequential eprom locations without address transactions across the pbus for each read or write. 8
8xc196mc absolute maximum ratings ambient temperature under bias b 40 cto a 85 c storage temperature b 65 cto a 150 c voltage from ea or v pp to v ss or angnd a 13.00v voltage on v pp or eq to v ss or angnd b 0.5v to 13.0v voltage on any other pin to v ss or angnd b 0.5v to a 7.0v (1) power dissipation 1.5w (2) notes: 1. this includes v pp and ea on rom or cpu only devices. 2. power dissipation is based on package heat transfer lim- itations, not device power consumption. notice: this data sheet contains preliminary infor- mation on new products in production. the specifica- tions are subject to change without notice. verify with your local intel sales office that you have the latest data sheet before finalizing a design. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. operating conditions symbol description min max units t a ambient temperature under bias b 40 a 85 c v cc digital supply voltage 4.50 5.50 v v ref analog supply voltage 4.00 5.50 v f osc oscillator frequency 8 16 mhz note: angnd and v ss should be nominally at the same potential. also v ss and v ss1 must be at the same potential. dc electrical characteristics (over specified operating conditions) symbol parameter min max units test conditions v il input low voltage b 0.5 0.3 v cc v v ih input high voltage 0.7 v cc v cc a 0.5 v v ol output low voltage 0.3 v i ol e 200 m a port 2 and 5, p6.6, p6.7, 0.45 v i ol e 3.2 ma clkout 1.5 v i ol e 7ma v ol1 output low voltage on port 3/4 1.0 v i ol e 15 ma v ol2 output low voltage on 0.45 v i ol e 10 ma port 6.0 6.5 v oh output high voltage v cc b 0.3 v i oh eb 200 m a v cc b 0.7 v i oh eb 3.2 ma v cc b 1.5 v i oh eb 7ma v th a v th b hysteresis voltage width on 0.2 v typical reset 9
8xc196mc dc electrical characteristics (over specified operating conditions) (continued) symbol parameter min typ max units test conditions i li input leakage current on all input g 10 m a0v k v in k v cc 0.3v (in reset) only pins i li1 input leakage current on port0 g 3 m a0v k v in k v ref and port1 i il input low current on bd ports b 70 m av in e 0.3 v cc (note 1) i il1 input low current on p5.4 and b 7 ma 0.2 v cc p2.6 during reset i oh output high current on p5.4 and b 2 ma 0.7 v cc p2.6 during reset i cc active mode current in reset 50 70 ma xtal1 e 16 mhz, i ref a/d conversion reference current 2 5 ma v cc e v pp e v ref e 5.5v i idl idle mode current 15 30 ma i pd power-down mode current 5 50 m av cc e v pp e v ref e 5.5v r rst reset pin pullup resistor 6k 65k x c s pin capacitance (any pin to v ss )10pff test e 1.0 mhz notes: 1. bd (bidirectional ports) include: p2.0 p2.7, except p2.6 p3.0 p3.7 p4.0 p4.7 p5.0 p5.3 p5.5 p5.7 2. during normal (non-transient) conditions, the following total current limits apply: p6.0 p6.5 i ol :40ma i oh :28ma p3 i ol :90ma i oh :42ma p4 i ol :90ma i oh :42ma p5, clkout i ol :35ma i oh :35ma p2, p6.6, p6.7 i ol :63ma i oh :63ma 10
8xc196mc explanation of ac symbols each symbol is two pairs of letters prefixed by ``t'' for time. the characters in a pair indicate a signal and its condition, respectively. symbols represent the time between the two signal/condition points. conditions: signals: h e high l e low v e valid x e no longer valid z e floating a e address b e bhe c e clkout d e data g e buswidth h e hold ha e hlda l e ale/adv br e breq rerd wewr /wrh /wrl x e xtal1 y e ready q e data out ac electrical characteristics (over specified operating conditions) test conditions: capacitive load on all pins e 100 pf, rise and fall times e 10 ns, f osc e 16 mhz. the system must meet the following specifications to work with the 87c196mc: symbol parameter min max units notes f xtal frequency on xtal1 8 16 mhz 3 t osc 1/f xtal 62.5 125 ns t avyv address valid to ready setup 2 t osc b 75 ns t llyv ale low to ready setup t osc b 70 ns 4 t ylyh not ready time no upper limit ns t clyx ready hold after clkout low 0 t osc b 30 ns 1 t llyx ready hold after ale low t osc b 15 2 t osc b 40 ns 1 t avgv address valid to buswidth setup 2 t osc b 75 ns t llgv ale low to buswidth setup t osc b 60 ns 4 t clgx buswidth hold after clkout low 0 ns t avdv address valid to input data valid 3 t osc b 55 ns 2 t rldv rd active to input data valid t osc b 22 ns 2 t cldv clkout low to input data valid t osc b 50 ns t rhdz end of rd to input data float t osc ns t rxdx data hold after rd inactive 0 ns notes: 1. if max is exceeded, additional wait states will occur. 2. if wait states are used, add 2 t osc * n, where n e number of wait states. 3. testing performed at 8 mhz. however, the device is static by design and will typically operate below 1 hz. 4. these timings are included for compatibility with older b 90 and bh products. they should not be used for newer high- speed designs. 11
8xc196mc ac electrical characteristics (continued) test conditions: capacitive load on all pins e 100 pf, rise and fall times e 10 ns, f osc e 16 mhz. the 87c196mc will meet the following timing specifications: symbol parameter min max units notes t xhch xtal1 to clkout high or low 30 110 ns t clcl clkout cycle time 2 t osc ns t chcl clkout high period t osc b 10 t osc a 15 ns t cllh clkout falling edge to ale rising b 515ns t llch ale falling edge to clkout rising b 20 15 ns t lhlh ale cycle time 4 t osc ns 3 t lhll ale high period t osc b 10 t osc a 10 ns t avll address setup to ale falling edge t osc b 15 ns t llax address hold after ale falling t osc b 40 ns t llrl ale falling edge to rd falling t osc b 30 ns t rlcl rd low to clkout falling edge 4 30 ns t rlrh rd low period t osc b 5t osc a 25 ns 3 t rhlh rd rising edge to ale rising edge t osc t osc a 25 ns 1 t rlaz rd low to address float 5 ns t llwl ale falling edge to wr falling t osc b 10 ns t clwl clkout low to wr falling edge 0 25 ns t qvwh data stable to wr rising edge t osc b 23 ns t chwh clkout high to wr rising edge b 10 15 ns t wlwh wr low period t osc b 30 ns 3 t whqx data hold after wr rising edge t osc b 25 ns t whlh wr rising edge to ale rising edge t osc b 10 t osc a 15 ns 1 t whbx bhe , inst hold after wr rising t osc b 10 ns t whax ad8 15 hold after wr rising t osc b 30 ns 2 t rhbx bhe , inst hold after rd rising t osc b 10 ns t rhax ad8 15 hold after rd rising t osc b 30 ns 2 notes: 1. assuming back to back cycles. 2. 8-bit bus only. 3. if wait states are used, add 2 t osc * n, where n e number of wait states. 12
8xc196mc system bus timings 270946 5 13
8xc196mc ready timings (one wait state) 270946 6 buswidth timings 270946 7 14
8xc196mc external clock drive symbol parameter min max units 1/t xlxl oscillator frequency 8 16.0 mhz t xlxl oscillator period 62.5 125 ns t xhxx high time 22 ns t xlxx low time 22 ns t xlxh rise time 10 ns t xhxl fall time 10 ns external crystal connections 270946 14 note: keep oscillator components close to chip and use short, direct traces to xtal1, xtal2 and v ss . when using crystals, c1 e 20 pf, c2 e 20 pf. when using ceramic resonators, consult manufacturer for recom- mended circuitry. external clock connections 270946 15 * required if ttl driver used. not needed if cmos driver is used. external clock drive waveforms 270946 8 an external oscillator may encounter as much as a 100 pf load at xtal1 when it starts-up. this is due to interaction between the amplifier and its feedback capacitance. once the external signal meets the v il and v ih specifications the capacitance will not exceed 20 pf. ac testing input, output waveforms 270946 9 ac testing inputs are driven at 3.5v for a logic ``1'' and 0.45v for a logic ``0''. timing measurements are made at 2.0v for a logic ``1'' and 0.8v for a logic ``0''. float waveforms 270946 10 for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded v oh /v ol level occurs i ol /i oh e s g 15 ma. 15
8xc196mc a to d characteristics the sample and conversion time of the a/d convert- er in the 8-bit or 10-bit modes is programmed by loading a byte into the ad e time special function register. this allows optimizing the a/d operation for specific applications. the ad e time register is functional for all possible values, but the accuracy of the a/d converter is only guaranteed for the times specificed in the operating conditions table. the value loaded into ad e time bits 5, 6, 7 deter- mines the sample time, t sam , and is calculated us- ing the following formula: sam e (t sam c f osc ) b 2 8 t sam e sample time, m s f osc e processor frequency, mhz sam e value loaded into ad e time bits 5, 6, 7 sam must be in the range 1 through 7. the value loaded into ad e time bits 0 5 deter- mines the conversion time, t conv , and is calculated using the following formula: conv e (t conv c f osc ) b 3 2b b 1 t conv e conversion time, m s f osc e processor frequency, mhz b e 8 for 8-bit conversion b e 10 for 10-bit conversion conv e value loaded into ad e time bits 0 5 conv must be in the range 2 through 31. the converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of v ref . v ref must be close to v cc since it supplies both the resistor ladder and the analog portion of the convert- er and input port pins. there is also an ad e test sfr that allows for conversion on angnd and v ref as well as adjusting the zero offset. the abso- lute error listed is without doing any adjustments. a/d converter specification the specifications given assume adherence to the operating conditions section of this data sheet. test- ing is performed with v ref e 5.12v and 16.0 mhz operating frequency. after a conversion is started, the device is placed in the idle mode until the con- version is complete. 16
8xc196mc 10-bit mode a/d operating conditions symbol description min max units t a ambient temperature b 40 a 85 c v cc digital supply voltage 4.50 5.50 v v ref analog supply voltage 4.00 5.50 v (1) t sam sample time 1.0 m s (2) t conv conversion time 10.0 20.0 m s (2) f osc oscillator frequency 8.0 16.0 mhz notes: angnd and v ss should nominally be at the same potential. 1. v ref must be within 0.5v of v cc . 2. the value of ad e time is selected to meet these specifications. 10-bit mode a/d characteristics (over specified operating conditions) parameter typical (1) min max units * resolution 1024 1024 levels 10 10 bits absolute error 0 g 4 lsbs full scale error 0.25 g 0.5 lsbs zero offset error 0.25 g 0.5 lsbs non-linearity 1.0 g 2.0 g 4 lsbs differential non-linearity l b 1 a 2 lsbs channel-to-channel matching g 0.1 0 g 1.0 lsbs repeatability g 0.25 0 lsbs temperature coefficients: offset 0.009 lsb/c full scale 0.009 lsb/c differential non-linearity 0.009 lsb/c off isolation b 60 db (2, 3) feedthrough b 60 db (2) v cc power supply rejection b 60 db (2) input series resistance 750 2k x (4) voltage on analog input pin angnd b 0.5 v ref a 0.5 v (5, 6) sampling capacitor 3 pf dc input leakage g 10 g 3.0 m a notes: * an ``lsb'', as used here has a value of approximately 5 mv. (see embedded microcontrollers and processors handbook for a/d glossary of terms). 1. these values are expected for most parts at 25 c but are not tested or guaranteed. 2. dc to 100 khz. 3. multiplexer break-before-make is guaranteed. 4. resistance from device pin, through internal mux, to sample capacitor. 5. these values may be exceeded if the pin current is limited to g 2 ma. 6. applying voltages beyond these specifications will degrade the accuracy of other channels being converted. 7. all conversions performed with processor in idle mode. 17
8xc196mc 8-bit mode a/d operating conditions symbol description min max units t a ambient temperature b 40 a 85 c v cc digital supply voltage 4.50 5.50 v v ref analog supply voltage 4.00 5.50 v (1) t sam sample time 1.0 m s (2) t conv conversion time 7.0 20.0 m s (2) f osc oscillator frequency 8.0 16.0 mhz notes: angnd and v ss should nominally be at the same potential. 1. v ref must be within 0.5v of v cc . 2. the value of ad e time is selected to meet these specifications. 8-bit mode a/d characteristics (over the above operating conditions) parameter typical (1) min max units * resolution 256 256 level 8 8 bits absolute error 0 g 1 lsbs full scale error g 0.5 lsbs zero offset error g 0.5 lsbs non-linearity 0 g 1 lsbs differential non-linearity l b 1 a 1 lsbs channel-to-channel matching 0 g 1.0 lsbs repeatability g 0.25 lsbs temperature coefficients: offset 0.003 lsb/c full scale 0.003 lsb/c differential non-linearity 0.003 lsb/c off isolation b 60 db (2, 3) feedthrough b 60 db (2) v cc power supply rejection b 60 db (2) input series resistance 750 2k x (4) voltage on analog input pin v ss b 0.5 v ref a 0.5 v (5, 6) sampling capacitor 3 pf dc input leakage g 10 g 3.0 m a notes: * an ``lsb'' as used here, has a value of approximately 20 mv. (see embedded microcontrollers and processors handbook for a/d glossary of terms). 1. these values are expected for most parts at 25 c but are not tested or guaranteed. 2. dc to 100 khz. 3. multiplexer break-before-make is guaranteed. 4. resistance from device pin, through internal mux, to sample capacitor. 5. these values may be exceeded if the pin current is limited to g 2 ma. 6. applying voltages beyond these specifications will degrade the accuracy of other channels being converted. 7. all conversions performed with processor in idle mode. 18
8xc196mc eprom specifications operating conditions symbol description min max units t a ambient temperature during programming 20 30 c v cc supply voltage during programming 4.5 5.5 v (1) v ref reference supply voltage during programming 4.5 5.5 v (1) v pp programming voltage 12.25 12.75 v (2) v ea ea pin voltage 12.25 12.75 v (2) f osc oscillator frequency during auto 6.0 8.0 mhz and slave mode programming t osc oscillator frequency during 6.0 12.0 mhz run-time programming notes: 1. v cc and v ref should nominally be at the same voltage during programming. 2. v pp and v ea must never exceed the maximum specification, or the device may be damaged. 3. v ss and angnd should nominally be at the same potential (0v). 4. load capacitance during auto and slave mode programming e 150 pf. ac eprom programming characteristics symbol parameter min max units t shll reset high to first pale low 1100 t osc t lllh pale pulse width 50 t osc t avll address setup time 0 t osc t llax address hold time 100 t osc t pldv prog low to word dump valid 50 t osc t phdx word dump data hold 50 t osc t dvpl data setup time 0 t osc t pldx data hold time 400 t osc t plph (1) prog pulse width 50 t osc t phll prog high to next pale low 220 t osc t lhpl pale high to prog low 220 t osc t phpl prog high to next prog low 220 t osc t phil prog high to ainc low 0 t osc t ilih ainc pulse width 240 t osc t ilvh pver hold after ainc low 50 t osc t ilpl ainc low to prog low 170 t osc t phvl prog high to pver valid 220 t osc note: 1. this specification is for the word dump mode. for programming pulses, use the modified quick pulse algorithm. 19
8xc196mc dc eprom programming characteristics symbol parameter min max units i pp v pp supply current (when programming) 100 ma note: do not apply v pp until v cc is stable and within specifications and the oscillator/clock has stabilized or the device may be damaged. slave programming mode data program mode with single program pulse 2709461 11 note: p3.0 must be high (``1'') 20
8xc196mc slave programming mode in word dump with auto increment 270946 12 note: p3.0 must be low (``0'') slave programming mode timing in data program with repeated prog pulse and auto increment 270946 13 21
8xc196mc 87c196mc design considerations when an indirect shift during divide occurs the upper 3 bits of the shift count are not masked completely. if the shift count register has the value 32 * n where n e 1, 3, 5 or 7, the operand will be shifted 32 times. this should have resulted in no shift taking place. data sheet revision history this data sheet (270946-004) is valid for devices with a ``b'' at the end of the topside tracking number. data sheets are changed as new device information becomes available. verify with your local intel sales office that you have the latest version before finaliz- ing a design or ordering devices. the following important differences exist between this data sheet (270946-002) and the previous ver- sion (270946-003): 1. the data sheet was reorganized to standard for- mat. 2. added 83c196mc device. 3. added package thermal characteristics. 4. added note on missing pins on sdip package. 5. removed sfr maps (now in user's manual). 6. added note on t llyv and t llgv specifications. 7. changed 10-bit mode t conv (min) to 10.0 m s from 15.0 m s. 8. changed 10-bit mode t conv (max) to 20.0 m s from 18.0 m s. 9. changed vref (min) in 8- and 10-bit mode to 4.0v from 4.5v. the following important differences exist between data sheet 270946-003 and the previous version (270946-002): 1. the data sheet title was changed to better reflect the purpose of the 87c196mc as an ac inverter/ dc brushless motor control microcontroller. 2. the standard temperature range for this part now covers b 40 cto a 85 c. 3. extint function description now includes wg e protect (1fceh) as the name and ad- dress of the register used to select positive/neg- ative or high/low detection for extint. 4. the memory range 01f00h 01fbfh was added to the sfr map as reserved. 5. i il changed from b 60 m ato b 70 m a. 6. i ref changed from 5 ma to 2 ma maximum and the typical specification was removed. 7. the ready description of the ready timings (one wait state) graphic was modified to denote the shifting of the leading edge of ready versus frequency. at 16 mhz the falling edge of ready occurs before the falling edge of ale. 8. ac testing input, output waveform was changed to reflect inputs driven at 3.5v for a logic ``1'' and .45v for a logic ``0'' and timing measurements made at 2.0v for a logic ``1'' and 0.8v for a logic ``0''. 9. float waveform was changed from i ol /i oh e g 15 ma to i ol /i oh s g 15 ma 10. ad e time register for 10-bit conversions was changed from 0c7h to 0d8h. the number of sample time states was changed from 24 to 25 states, the conversion time states was changed from 80 to 240 states, and the total conversion time for ad e time e d8h replaced the total conversion time for ad e time e c7h. 11. the number of sample time states for an 8-bit conversion was changed from 20 states to 21 states. 12. there is a single entry in the errata section of this version of the data sheet concerning the results of an indirect shift during divide. the following important differences exist between this data sheet (270946-002) and the previous ver- sion (270946-001): 1. t a ambient temperature under bias min changed from b 20 cto b 40 c. 2. i ref a/d conversion reference current max changed from 5 ma to 2 ma. 3. testing levels changed from ttl values to cmos values. 4. a/d input series resistance max changed from 1.2 k x to 2 k x . 22

▲Up To Search▲

Price & Availability of EE87C196MC

	To Download EE87C196MC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .